Application Specific Integrated Circuits Addison Wesley Michael John Circuits - Addison Wesley Michael John Sebastian terney.info Michael John Sebastian Smith. This course is based on ASICs the book. Application-Specific Integrated Circuits. Michael J. S. Smith. VLSI Design Series. Title Application-Specific Integrated Circuits; Author(s) Michael John Sebastian Smith; Publisher: Addison-Wesley Professional; 1 edition (June 20, ).
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Full text of "Application Specific Integrated Circuits Addison Wesley Michael John Sebastian Smith" . Both of these examples are specific to an application ( shades of an ASIC) See also P. B. Denyer and S. G. Smith, Serial-Data Computation. . waveforms showing the definition of the falling propagation delay, t PDf. ASICs by M J Smith - Free ebook download as PDF File .pdf), Text File .txt) application-specific integrated circuit at least that is what the acronym stands for. Application specific integrated circuits (ASICs) are usually non standard .  Michael John Sebastian Smith, “Application-Specific. Integrated.
The first half-dozen or so layers define the transistors. The last half-dozen or so layers define the metal wires between the transistors the interconnect. A full-custom IC includes some possibly all logic cells that are customized and all mask layers that are customized. A microprocessor is an example of a full-custom ICdesigners spend many hours squeezing the most out of every last square micron of microprocessor chip space by hand.
Customizing all of the IC features in this way allows designers to include analog circuits, optimized memory cells, or mechanical structures on an IC, for example. Full-custom ICs are the most expensive to manufacture and to design. The manufacturing lead time the time it takes just to make an ICnot including design time is typically eight weeks for a full-custom IC.
These specialized full-custom ICs are often intended for a specific application, so we might call some of them full-custom ASICs. We shall discuss full-custom ASICs briefly next, but the members of the IC family that we are more interested in are semicustom ASICs , for which all of the logic cells are predesigned and some possibly all of the mask layers are customized.
Using predesigned cells from a cell library makes our lives as designers much, much easier. There are two types of semicustom ASICs that we shall cover: Following this we shall describe the programmable ASICs , for which all of the logic cells are predesigned and none of the mask layers are customized. There are two types of programmable ASICs: This means the designer abandons the approach of using pretested and precharacterized cells for all or part of that design.
It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design. This might be because existing cell libraries are not fast enough, or the logic cells are not small enough or consume too much power.
You may need to use full-custom design if the ASIC technology is new or so specialized that there are no existing cell libraries or because the ASIC is so specialized that some circuits must be custom designed. Bipolar technology has historically been used for precision analog functions. There are some fundamental reasons for this.
In all integrated circuits the matching of component characteristics between chips is very poor, while the matching of characteristics between components on the same chip is excellent.
The three transistors are all the same size and are constructed in an identical fashion. Transistors Tl and T2 are located adjacent to each other and have the same orientation. Transistor T3 is the same size as Tl and T2 but is located on the other side of the chip from Tl and T2 and has a different orientation.
ICs are made in batches called wafer lots. A wafer lot is a group of silicon wafers that are all processed together. Usually there are between 5 and 30 wafers in a lot.
Each wafer can contain tens or hundreds of chips depending on the size of the IC and the wafer. If we were to make measurements of the characteristics of transistors Tl, T2, and T3 we would find the following: We say that the transistors match well or the tracking between devices is excellent. The matching will depend on how far apart the two ICs are on the wafer. For many analog designs the close matching of transistors is crucial to circuit operation. For these circuit designs pairs of transistors are used, located adjacent to each other.
Device physics dictates that a pair of bipolar transistors will always match more precisely than CMOS transistors of a comparable size. Bipolar technology has historically been more widely used for full-custom analog design because of its improved precision.
Despite its poorer analog properties, the use of CMOS technology for analog functions is increasing. There are two reasons for this. The second reason is that increased levels of integration require mixing analog and digital functions on the same IC: Circuit designers, using clever new techniques, have been very successful in finding new ways to design analog CMOS circuits that can approach the accuracy of bipolar analog designs. The standard-cell areas also called flexible blocks in a CBIC are built of rows of standard cellslike a wall built of bricks.
The standard-cell areas may be used in combination with larger predesigned cells, perhaps microcontrollers or even microprocessors, known as megacells. However, the standard cells can be placed anywhere on the silicon; this means that all the mask layers of a CBIC are customized and are unique to a particular customer.
The advantage of CBICs is that designers save time, money, and reduce risk by using a predesigned, pretested, and precharacterized standard-cell library. In addition each standard cell can be optimized individually.
During the design of the cell library each and every transistor in every standard cell can be chosen to maximize speed or minimize area, for example.
The disadvantages are the time or expense of designing or downloading the standard-cell library and the time needed to fabricate all layers of the ASIC for each new design. The important features of this type of ASIC are as follows: The flexible block contains rows of standard cells. This is what you might see through a low-powered microscope looking down on the die of Figure 1.
The small squares around the edge of the die are bonding pads that are connected to the pins of the ASIC package. Each standard cell in the library is constructed using full-custom design methods, but you can use these predesigned and precharacterized circuits without having to do any full-custom design yourself. This design style gives you the same performance and flexibility advantages of a full-custom ASIC but reduces design time and reduces risk. Standard cells are designed to fit together like bricks in a wall.
Standard cells are stacked like bricks in a wall; the abutment box AB defines the edges of the brick. The difference between the bounding box BB and the AB is the area of overlap between the bricks. Power supplies labeled VDD and GND run horizontally inside a standard cell on a metal layer that lies above the transistor layers.
Each different shaded and labeled pattern represents a different layer. This standard cell has center connectors the three squares, labeled Al, Bl, and Z that allow the cell to connect to others. Standard-cell design allows the automation of the process of assembling an ASIC. Groups of standard cells fit horizontally together to form rows.
The rows stack vertically to form flexible rectangular blocks which you can reshape during design. You may then connect a flexible block built from several rows of standard cells to other standard-cell blocks or other full-custom logic blocks.
For example, you might want to include a custom interface to a standard, predesigned microcontroller together with some memory. The microcontroller block may be a fixed-size megacell, you might generate the memory using a memory compiler, and the custom logic and memory controller will be built from flexible standard-cell blocks, shaped to fit in the empty spaces on the chip. Both cell-based and gate-array ASICs use predefined cells, but there is a differencewe can change the transistor sizes in a standard cell to optimize speed and performance, but the device sizes in a gate array are fixed.
This results in a trade-off in performance and area in a gate array at the silicon level. The trade-off between area and performance is made at the library level for a standard-cell ASIC. This allows wires to cross over different layers in the same way that we use copper traces on different layers on a printed-circuit board.
In a two-level metal CMOS technology, connections to the standard-cell inputs and outputs are usually made using the second level of metal metal2 , the upper level of metal at the tops and bottoms of the cells. In a three-level metal technology, connections may be internal to the logic cell as they are in Figure 1. This allows for more sophisticated routing programs to take advantage of the extra metal layer to route interconnect over the top of the logic cells.
A connection that needs to cross over a row of standard cells uses a feedthrough. The term feedthrough can refer either to the piece of metal that is used to pass a signal through a cell or to a space in a cell waiting to be used as a feedthrough very confusing. In both two-level and three-level metal technology, the power buses VDD and GND inside the standard cells normally use the lowest closest to the transistors layer of metal metal 1. The width of each row of standard cells is adjusted so that they may be aligned using spacer cells.
The power buses, or rails, are then connected to additional vertical power rails using row-end cells at the aligned ends of each standard-cell block. If the rows of standard cells are long, then vertical power rails can also be run in metal2 through the cell rows using special power cells that just connect to VDD and GND. Usually the designer manually controls the number and width of the vertical power rails connected to the standard-cell blocks during physical design.
The use of regularly shaped standard cells, such as the one in Figure 1. This ASIC uses two separate layers of metal interconnect metal 1 and metal2 running at right angles to each other like traces on a printed-circuit board. Interconnections between logic cells uses spaces called channels between the rows of cells. ASICs may have three or more layers of metal allowing the cell rows to touch with the interconnect running over the top of the cells.
All the mask layers of a CBIC are customized. Megacells are usually supplied by an ASIC or library company complete with behavioral models and some way to test them a test strategy.
Since all mask layers on a standard-cell design are customized, memory design is more efficient and denser than for gate arrays. For logic that operates on multiple signals across a data busa datapath DP the use of standard cells may not be the most efficient ASIC design style. Some ASIC library companies provide a datapath compiler that automatically generates datapath logic. A datapath library typically contains cells such as adders, subtracters, multipliers, and simple arithmetic and logical units ALUs.
The connectors of datapath library cells are pitch-matched to each other so that they fit together. Connecting datapath cells to form a datapath usually, but not always, results in faster and denser layout than using standard cells or a gate array. Standard-cell and gate-array libraries may contain hundreds of different logic cells, including combinational functions NAND, NOR, AND, OR gates with multiple inputs, as well as latches and flip-flops with different combinations of reset, preset and clocking options.
The ASIC library company provides designers with a data book in paper or electronic form with all of the functional descriptions and timing information for each library element. The predefined pattern of transistors on a gate array is the base array , and the smallest element that is replicated to make the base array like an M. Escher drawing, or tiles on a floor is the base cell sometimes called a primitive cell. Only the top few layers of metal, which define the interconnect between transistors, are defined by the designer using custom masks.
To distinguish this type of gate array from other types of gate array, it is often called a masked gate array MGA. The designer chooses from a gate-array library of predesigned and precharacterized logic cells. The logic cells in a gate-array library are often called macros. The reason for this is that the base-cell layout is the same for each logic cell, and only the interconnect inside cells and between cells is customized, so that there is a similarity between gate-array macros and a software macro.
Inside IBM, gate-array macros are known as books so that books are part of a library , but unfortunately this descriptive term is not very widely used outside IBM. We can complete the diffusion steps that form the transistors and then stockpile wafers sometimes we call a gate array a prediffused array for this reason. Since only the metal interconnections are unique to an MGA, we can use the stockpiled wafers for different customers as needed.
Using wafers prefabricated up to the metallization steps reduces the time needed to make an MGA, the turnaround time , to a few days or at most a couple of weeks. The hyphenation of these terms when they are used as adjectives explains their construction. For example, in the term channeled gate-array architecture, the gate array is channeled , as will be explained.
There are two common ways of arranging or arraying the transistors on a MGA: The channeled gate array was the first to be developed, but the channelless gate-array architecture is now more widely used. A structured or embedded gate array can be either channeled or channelless but it includes or embeds a custom block. The important features of this type of MGA are: The spaces between rows of the base cells are set aside for interconnect.
A channeled gate array is similar to a CBICboth use rows of cells separated by channels used for interconnect. One difference is that the space for interconnect between rows of cells are fixed in height in a channeled gate array, whereas the space between rows of cells may be adjusted in a CBIC.
The important features of this type of MGA are as follows: The core area of the die is completely filled with an array of base cells the base array. Instead we route over the top of the gate-array devices. We can do this because we customize the contact layer that defines the connections between metal 1, the first layer of metal, and the transistors.
When we use an area of transistors for routing in a channelless array, we do not make any contacts to the devices lying underneath; we simply leave the transistors unused. The logic densitythe amount of logic that can be implemented in a given silicon areais higher for channelless gate arrays than for channeled gate arrays.
This is usually attributed to the difference in structure between the two types of array. In fact, the difference occurs because the contact mask is customized in a channelless gate array, but is not usually customized in a channeled gate array. This leads to denser cells in the channelless architectures. Customizing the contact layer in a channelless gate array allows us to increase the density of gate-array cells because we can route over the top of unused contact sites.
One of the disadvantages of the MGA is the fixed gate-array base cell. This makes the implementation of memory, for example, difficult and inefficient. In an embedded gate array we set aside some of the IC area and dedicate it to a specific function. This embedded area either can contain a different base cell that is more suitable for building memory cells, or it can contain a complete circuit block, such as a microcontroller. The important features of this type of MGA are the following: The rest of the die is filled with an array of base cells.
An embedded gate array gives the improved area efficiency and increased performance of a CBIC but with the lower cost and faster turnaround of an MGA. One disadvantage of an embedded gate array is that the embedded function is fixed.
For example, if an embedded gate array contains an area set aside for a 32 k-bit memory, but we only need a 16 k-bit memory, then we may have to waste half of the embedded memory function. However, this may still be more efficient and cheaper than implementing a 32 k-bit memory using macros on a SOG array. ASIC vendors may offer several embedded gate array structures containing different memory types and sizes as well as a variety of embedded functions. However, PLDs may be configured or programmed to create a part customized to a specific application, and so they also belong to the family of ASICs.
PLDs use different technologies to allow programming of the device. The macrocells typically consist of programmable array logic followed by a flip-flop or latch. The macrocells are connected using a large programmable interconnect block.
A masked ROM is a regular array of transistors permanently programmed using custom mask patterns. An embedded masked ROM is thus a large, specialized, logic cell. The same programmable technologies used to make ROMs can be applied to more flexible logic structures. By using the programmable devices in a large array of AND gates and an array of OR gates, we create a family of flexible and programmable logic devices called logic arrays. A PAL can also include registers flip-flops to store the current state information so that you can use a PAL to make a complete state machine.
This type of logic array is called a programmable logic array PLA. We shall examine these features in detail in Chapters All FPGAs contain a regular structure of programmable basic logic cells surrounded by programmable interconnect.
The exact type, size, and number of the programmable basic logic cells varies tremendously. The steps are listed below numbered to correspond to the labels in Figure 1.
Design entry. Logic synthesis. System partitioning. Divide a large system into ASIC-sized pieces. Prelayout simulation. Check to see if the design functions correctly. Arrange the blocks of the netlist on the chip. Decide the locations of cells in a block. It is now an old design but a very important example because it was one of the first workstations to make extensive use of ASICs to achieve the following: The rest of the system is partitioned into three more ASICs: TABLE 1.
The important point to notice, though, is that there is a lot more to microelectronic system design than designing the ASICsless than one-third of the tools listed in Table 1. Using ASIC technology reduces the motherboard to about the size of a piece of paper 8. Some information in Section 1. The first is Concept to System: Bechtolsheim, T. Westberg, M. Insley, and J. Ludemann of Sun Microsystems; J-H.
Huang and D. Boyle of LSI Logic. This is an LSI Logic publication. Beyond the 3M Horizon, A. Bechtolsheim and E. Frank, a Sun Microsystems publication. I did not include these as references since they are impossible to obtain now, but I would like to give credit to Andy Bechtolsheim and the Sun Microsystems and LSI Logic engineers.
To make an economic comparison between these alternatives, we consider the ASIC itself as a product and examine the components of product cost: Making cost comparisons is dangerouscosts change rapidly and the semiconductor industry is notorious for keeping its costs, prices, and pricing strategy closely guarded secrets.
The figures in the following sections are approximate and used to illustrate the different components of cost. Part costs vary enormouslyyou can pay anywhere from a few dollars to several hundreds of dollars for an ASIC. For example, a 0. Is the increased flexibility of an FPGA worth the extra cost per part?
Given that an MGA or CBIC is specially tailored for each customer, there are extra hidden costs associated with this step that we should consider. To make a true comparison between the different ASIC technologies, we shall quantify some of these costs. However, the fixed costs amortized per product sold fixed costs divided by products sold decrease as sales volume increases. Variable costs include the cost of the parts used in the product, assembly costs, and other manufacturing costs.
Let us look more closely at the parts in a product. We shall discuss these extra costs in more detail in Sections 1. The total part costs of two alternative types of ASIC are equal at the break-even volume. In Figure 1. The break-even volume between two technologies is the point at which the total cost of parts are equal.
These numbers are very approximate. We shall describe how to calculate the fixed part costs next.
These costs can vary wildly. The training cost includes the cost of the time to learn any new electronic design automation EDA system.
For example, a new FPGA design system might require a few days to learn; a new gate-array or cell-based design system might require taking a course. Next we consider the hardware and software cost for ASIC design. We try to measure productivity of an ASIC designer in gates or transistors per day. This is like trying to predict how long it takes to dig a hole, and the number of gates per day an engineer averages varies wildly.
This means that it is often easier to learn and use than semicustom ASIC design tools. Every ASIC has to pass a production test to make sure that it works. With modern test tools the generation of any test circuits on each ASIC that are needed for production testing can be automatic, but it still involves a cost for design for test.
An FPGA is tested by the manufacturer before it is sold to you and before you program it. You do have to pay for any programming costs for an FPGA, but we can include these in the hardware and software cost. The production test uses sets of test inputs called test vectors , often many thousands of them. Most ASIC vendors require simulation to generate test vectors and test programs for production testing, and will charge for a test-program development cost.
If you commit to high volumes above , parts , the vendor may waive the NRE charge. The NRE charge may also include the costs of software tools, design verification, and prototype samples. If your design does not work the first time, you have to complete a further design pass turn or spin that requires additional NRE charges. Normally you sign a contract sign off a design with an ASIC vendor that guarantees first-pass successthis means that if you designed your ASIC according to rules specified by the vendor, then the vendor guarantees that the silicon will perform according to the simulation or you get your money back.
This is why the difference between semicustom and full-custom design styles is so importantthe ASIC vendor will not and cannot guarantee your design will work if you use any full-custom design techniques. Nowadays it is almost routine to have an ASIC work on the first pass. However, if your design does fail, it is little consolation to have a second pass for free if your company goes bankrupt in the meantime.
Using this model, we can estimate the lost profit due to any delay. Suppose we have the following situation: The simple profit and revenue model of Figure 1. Despite the obvious problems with such a simple model how can we introduce the same product twice to compare the performance? In the electronics industry product lifetimes continue to shrink.
In the PC industry it is not unusual to have a product lifetime of 18 months or less. This means that it is critical to achieve a rapid design time or high product velocity with no delays.
The last fixed cost shown in Figure 1. When a company downloads an ASIC part, it needs to be assured that it will always have a back-up source, or second source , in case something happens to its first or primary source.
Established FPGA companies have a second source that produces equivalent parts. However, for all ASIC types, switching production to a second source will involve some cost.
This spreadsheet uses the terms and parameters defined below the figure. From to , 4-inch to 6-inch diameter wafers were common; equipment using 6-inch to 8-inch wafers was introduced between and ; the next step is the cm or inch wafer. The inch wafer will probably take us to Not all designs follow this law, but a large ASIC design seems to grow by a factor of 10 every 5 years close to Moores Law.
In a large ASIC design size was 10 k-gate, in a large design was about k-gate, in it will be 1 M-gate, in it will be 10 M-gate. The smaller the defect density the less likely there is to be a flaw on any one die. A single defect on a die is almost always fatal for that die.
Defect density usually increases with the number of steps in a process. A defect density of less than 1 cm 2 is typical and required for a submicron CMOS process. The yield is the fraction of die on a wafer that are good expressed as a percentage. Yield depends on the complexity and maturity of a process. A process may start out with a yield of close to zero for complex chips, which then climbs to above 50 percent within the first few months of production.
Within a year the yield has to be brought to around 80 percent for the average complexity ASIC for the process to be profitable. Yields of 90 percent or more are not uncommon. Of these parameters, the most variable and the most critical to control is the yield.
ASIC vendors that make and sell custom ASICs have huge fixed and variable costs associated with building and running fabrication facilities a fabrication plant is a fab. FPGA companies are typically fabless they do not own a fabthey must pass on the costs of the chip manufacture plus the profit margin of the chip manufacturer and the development cost of the FPGA structure in the FPGA part cost.
The profitability of any company in the ASIC business varies greatly. It varies with design size and declines over time. As such it will vary widely with time, process, yield, economic climate, ASIC size and complexity, and many other factors. Beyond the life of a process, prices can increase as demand falls and the fabrication equipment becomes harder to maintain. From Figure 1. The cost figures that we have used in this section are very approximate and can vary widely this means they may be off by a factor of 2 but probably are correct within a factor of ASIC companies do use spreadsheet models like these to calculate their costs.
Having decided if, and then which, ASIC technology is appropriate, you need to choose the appropriate cell library. Next we shall discuss the issues surrounding ASIC cell libraries: For a programmable ASIC the FPGA company supplies you with a library of logic cells in the form of a design kit , you normally do not have a choice, and the cost is usually a few thousand dollars.
The first choice, using an ASIC-vendor library , requires you to use a set of design tools approved by the ASIC vendor to enter and simulate your design.
You have to download the tools, and the cost of the cell library is folded into the NRE. For some reason the more common model in Japan is to use tools supplied by the ASIC vendor, but in the United States, Europe, and elsewhere designers want to choose their own tools. Perhaps this has to do with the relationship between customer and supplier being a lot closer in Japan than it is elsewhere. An ASIC vendor library is normally a phantom library the cells are empty boxes, or phantoms , but contain enough information for layout for example, you would only see the bounding box or abutment box in a phantom version of the cell in Figure 1.
After you complete layout you hand off a netlist to the ASIC vendor, who fills in the empty boxes phantom instantiation before manufacturing your chip. The second and third choices require you to make a download-or-build decision. This is called customer-owned tooling COT , pronounced see-oh-tee.
A library vendor normally develops a cell library using information about a process supplied by an ASIC foundry. If the cell library meets the foundry specifications, we call this a qualified cell library. These cell libraries are normally expensive possibly several hundred thousand dollars , but if a library is qualified at several foundries this allows you to shop around for the most attractive terms.
This means that downloading an expensive library can be cheaper in the long run than the other solutions for high- volume production. The third choice is to develop a cell library in-house. Many large computer and electronics companies make this choice.
Most of the cell libraries designed today are still developed in-house despite the fact that the process of library development is complex and very expensive. However created, each cell in an ASIC cell library must contain the following: The ASIC designer may not actually see the layout if it is hidden inside a phantom, but the layout will be needed eventually. The ASIC designer needs a high-level, behavioral model for each cell because simulation at the detailed timing level takes too long for a complete ASIC design.
For a NAND gate a behavioral model is simple. A multiport RAM model can be very complex. The designer may require Verilog and VHDL models in addition to the models for a particular logic simulator. It is too difficult, too time-consuming, and too expensive to build every cell in silicon and measure the cell delays.
Instead library engineers simulate the delay of each cell, a process known as characterization. Characterizing a standard-cell or gate-array library involves circuit extraction from the full-custom cell layout for each cell. The extracted schematic includes all the parasitic resistance and capacitance elements.
Then library engineers perform a simulation of each cell including the parasitic elements to determine the switching delays. The simulation models for the transistors are derived from measurements on special chips included on a wafer called process control monitors PCMs or drop-ins. Library engineers then use the results of the circuit simulation to generate detailed timing models for logic simulation. We shall cover timing models in Chapter All ASICs need to be production tested programmable ASICs may be tested by the manufacturer before they are customized, but they still need to be tested.
Simple cells in small or medium-size blocks can be tested using automated techniques, but large blocks such as RAM or multipliers need a planned strategy.
We shall discuss test in Chapter The cell schematic a netlist description describes each cell so that the cell designer can perform simulation for complex cells.
You may not need the detailed cell schematic for all cells, but you need enough information to compare what you think is on the silicon the schematic with what is actually on the silicon the layout this is a layout versus schematic LVS check. If the ASIC designer uses schematic entry, each cell needs a cell icon together with connector and naming information that can be used by design tools from different vendors.
One of the advantages of using logic synthesis Chapter 12 rather than schematic design entry is eliminating the problems with icons, connectors, and cell names. Logic synthesis also makes moving an ASIC between different cell libraries, or retargeting , much easier. In order to estimate the parasitic capacitance of wires before we actually complete any routing, we need a statistical estimate of the capacitance for a net in a given size circuit block. This usually takes the form of a look-up table known as a wire-load model.
We also need a routing model for each cell. Large cells are too complex for the physical design or layout tools to handle directly and we need a simpler representationa phantom of the physical layout that still contains all the necessary information.
The phantom may include information that tells the automated routing tool where it can and cannot place wires over the cell, as well as the location and types of the connections to the cell.
Table 1. ASICs use a library of predesigned and precharacterized logic cells. A full-custom pizza is built from scratch. You can customize all the layers of a CBIC pizza, but from a predefined selection, and it takes a while to cook. An MGA pizza uses precooked crusts with fixed sizes and you choose only from a few different standard types on a menu. This makes MGA pizza a little faster to cook and a little cheaper. An FPGA is rather like a frozen pizzayou download it at the supermarket in a limited selection of sizes and types, but you can put it in the microwave at home and it will be ready in a few minutes.
In each chapter we shall indicate the key concepts. You need a spreadsheet program such as Microsoft Excel for this problem. Build a spreadsheet, Break-even Analysis, to generate Figure 1. Derive equations for the break-even volumes there are three: For users of Excel-like spreadsheets use the XY scatter plot option.
Use the first column for the x -axis data. Find the new break-even volumes change the volume until the cost becomes the same for two technologies. Program your spreadsheet to automatically find the break-even volumes. Calculate the sensitivity of the break-even volumes to changes in the part costs and fixed costs.
There are three break-even volumes and each of these is sensitive to two part costs and two fixed costs. Express your answers in two ways: The costs in Figure 1.
What can you say from your answers if you are a defense contractor, primarily selling products in volumes of less than parts? What if you are a PC board vendor selling between 10, and , parts? Compare your answers with the figures for productivity in Section 1.
How accurate do you think productivity estimates are? Assuming, for this problem, a gate density of 1. The maximum die size is determined by the package cavity size; these are package-limited ASICs. Compare your answers with the maximum numbers of pins or leads on each package and comment. Now calculate the minimum number of gates that you can put in each package determined by the minimum die size. There is a well-known saying in the ASIC business: We lose money on every partbut we make it up in volume.
This has a serious side. Suppose Sumo Silicon currently has two customers: Big, who currently downloads 10, parts per week, and Ms. Smart, who currently downloads parts per week. A new customer, Ms. Teeny who is growing fast , wants to download parts per week. Sumo is currently running at wafer starts per week for Mr. Big and Ms. Sumo thinks they can get 50 cents more out of Mr. Big for his chips, but Ms. Smart wont pay any more.
We can calculate how much Sumo can afford to lose per chip if they want Ms. Teenys business really badly. What is Sumos current yield? How many good parts is Sumo currently producing per week? Routing: An electronics routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them.
Since the search space is large, this process will produce a "sufficient" rather than " globally optimal " solution. The output is a file which can be used to create a set of photomasks enabling a semiconductor fabrication facility , commonly called a 'fab' or 'foundry' to manufacture physical integrated circuits.
Placement and routing are closely interrelated and are collectively called place and route in electronics design. Sign-off: Given the final layout, circuit extraction computes the parasitic resistances and capacitances. In the case of a digital circuit , this will then be further mapped into delay information from which the circuit performance can be estimated, usually by static timing analysis. This, and other final tests such as design rule checking and power analysis collectively called signoff are intended to ensure that the device will function correctly over all extremes of the process, voltage and temperature.
When this testing is complete the photomask information is released for chip fabrication. These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process. The significant difference is that standard-cell design uses the manufacturer's cell libraries that have been used in potentially hundreds of other design implementations and therefore are of much lower risk than full custom design.
Standard cells produce a design density that is cost effective, and they can also integrate IP cores and static random-access memory SRAM effectively, unlike gate arrays. Gate-array and semi-custom design[ edit ] Microscope photograph of a gate-array ASIC showing the predefined logic cells and custom interconnections.
Gate array design is a manufacturing method in which diffused layers, each consisting transistors and other active devices , are predefined and electronics wafers containing such devices are "held in stock" or unconnected prior to the metallization stage of the fabrication process.
The physical design process defines the interconnections of these layers for the final device. For most ASIC manufacturers, this consists of between two and nine metal layers with each layer running perpendicular to the one below it. Non-recurring engineering costs are much lower than full custom designs, as photolithographic masks are required only for the metal layers.
Production cycles are much shorter, as metallization is a comparatively quick process; thereby accelerating time to market. Often difficulties in routing the interconnect require migration onto a larger array device with consequent increase in the piece part price. These difficulties are often a result of the layout EDA software used to develop the interconnect.
Pure, logic-only gate-array design is rarely implemented by circuit designers today, having been almost entirely replaced by field-programmable devices. Most prominent of such devices are field-programmable gate arrays FPGAs which can be programmed by the user and thus offer minimal tooling charges non-recurring engineering, only marginally increased piece part cost, and comparable performance.
Today, gate arrays are evolving into structured ASICs that consist of a large IP core like a CPU , digital signal processor units, peripherals , standard interfaces , integrated memories , SRAM , and a block of reconfigurable , uncommitted logic.
This shift is largely because ASIC devices are capable of integrating large blocks of system functionality, and systems on a chip SoCs require glue logic , communications subsystems such as networks on chip , peripherals and other components rather than only functional units and basic interconnection. In their frequent usages in the field, the terms "gate array" and "semi-custom" are synonymous when referring to ASICs.
Process engineers more commonly use the term "semi-custom", while "gate-array" is more commonly used by logic or gate-level designers. Main article: Full custom Microscope photograph of custom ASIC chipset showing gate-based design on top and custom circuitry on bottom By contrast, full-custom ASIC design defines all the photolithographic layers of the device.
Full-custom design is used for both ASIC design and for standard product design. As a Chegg Study subscriber, you can view available interactive solutions manuals for each of your classes for one low monthly price.
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