Microprocessor 8085 programming pdf


 

“Give and Take is brimming with life-changing insights. “One of the great secrets of life is that those who win mo Understanding / Microprocessors. M.E.,. LECTURER, DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING. 1. MICROPROCESSOR. PROGRAMS. Note: • Assembly language is specific to a given processor. • For e.g. assembly language of is different than that of Motorola microprocessor.

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Microprocessor 8085 Programming Pdf

INTRODUCTION TO MICROPROCESSOR Aim. To study the microprocessor the microprocessor and not accessible to programs. g) Flags. ISIS-II / MACRO ASSEMBLER OPERATOR'S MANUAL, When you .. the least expensive tools available for microprocessor programming. MICROPROCESSOR • Reference Book: – Ramesh S. Goankar, “ Microprocessor Architecture, Programming and Applications with ”, 5th Edition.

Skip to main content. Log In Sign Up. Arun Vinthan. What is a Microprocessor? It is a general term that describes all manipulation. What about micro? All of the components that made up the processor were now placed on a single piece of silicon. The size became several thousand times smaller and the speed became several hundred times faster. Definition of the Microprocessor The microprocessor is a programmable device that takes in numbers, performs on them arithmetic or logical operations according to the program stored in memory and then produces other numbers as a result. Definition Contd. The microprocessor can perform different sets of operations on the data it receives depending on the sequence of instructions supplied in the given program. By changing the program, the microprocessor manipulates the data in different ways. Each microprocessor is designed to execute a specific group of operations. This group of operations is called an instruction set.

The sign flag is set if the result has a negative sign i.

An Introduction to Microprocessor 8085 PDF

The auxiliary or half carry flag is set if a carry-over from bit 3 to bit 4 occurred. The parity flag is set according to the parity odd or even of the accumulator. The zero flag is set if the result of the operation was 0.

Lastly, the carry flag is set if a carry-over from bit 7 of the accumulator the MSB occurred. Some of them are followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. A NOP "no operation" instruction exists, but does not modify any of the registers or flags. Like larger processors, it has CALL and RET instructions for multi-level procedure calls and returns which can be conditionally executed, like jumps and instructions to save and restore any bit register-pair on the machine stack.

There are also eight one-byte call instructions RST for subroutines located at the fixed addresses 00h, 08h, 10h, These are intended to be supplied by external hardware in order to invoke a corresponding interrupt-service routine, but are also often employed as fast system calls. One sophisticated instruction is XTHL, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer.

For two-operand 8-bit operations, the other operand can be either an immediate value, another 8-bit register, or a memory cell addressed by the bit register pair HL. The only 8-bit ALU operations that can have a destination other than the accumulator are the unary incrementation or decrementation instructions, which can operate on any 8-bit register or on memory addressed by HL, as for two-operand 8-bit operations.

Direct copying is supported between any two 8-bit registers and between any 8-bit register and a HL-addressed memory cell, using the MOV instruction.

It also has a bit program counter and a bit stack pointer to memory replacing the 's internal stack. The accumulator stores the results of arithmetic and logical operations, and the flags register bits sign, zero, auxiliary carry, parity, and carry flags are set or cleared according to the results of these operations.

The sign flag is set if the result has a negative sign i. The auxiliary or half carry flag is set if a carry-over from bit 3 to bit 4 occurred.

The parity flag is set according to the parity odd or even of the accumulator. The zero flag is set if the result of the operation was 0. Lastly, the carry flag is set if a carry-over from bit 7 of the accumulator the MSB occurred.

Microprocessor Programs - PDF

Some of them are followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. A NOP "no operation" instruction exists, but does not modify any of the registers or flags. Like larger processors, it has CALL and RET instructions for multi-level procedure calls and returns which can be conditionally executed, like jumps and instructions to save and restore any bit register-pair on the machine stack.

There are also eight one-byte call instructions RST for subroutines located at the fixed addresses 00h, 08h, 10h, These are intended to be supplied by external hardware in order to invoke a corresponding interrupt-service routine, but are also often employed as fast system calls.

One sophisticated instruction is XTHL, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer.

8085 MICROPROCESSOR PROGRAMS

For two-operand 8-bit operations, the other operand can be either an immediate value, another 8-bit register, or a memory cell addressed by the bit register pair HL.

The simple view of RAM is that it is made up of registers that are made up of flip-flops or memory elements. ROM on the other hand uses diodes instead of the flip-flops to permanently hold the information. Select the right memory chip using part of the address bus.

Identify the memory location using the rest of the address bus. Access the data using the data bus. This buffer is a logic circuit that has three states: Logic 0, logic1, and high impedance. When this circuit is in high impedance mode it looks as if it is disconnected from the output completely. The first input behaves like the normal input for the circuit.

This latch has an input where the data comes in. It has an enable input and an output on which data comes out. Data is always present on the input and the output is always set to the contents of the latch. To avoid this, tri-state buffers are added at the input and output of the latch. The bar over WR means that this is an active low signal.

So, if WR is 0 the input data reaches the latch input. If WR is 1 the input of the latch looks like a wire connected to nothing. The RD signal controls the output in a similar manner. Then the microprocessor returns to its previous operations and continues.

Then using the appropriate Enable input we enable an individual memory register. What we have just designed is a memory with 4 locations and each location has 4 elements bits.

This memory would be called 4 X 4 [Number of location X number of bits per location]. Since we can never have more than one of these enables active at the same time, we can have them encoded to reduce the number of lines coming into the chip.

These encoded lines are the address lines for memory. The address is applied to the address decoder which generates a single Enable signal to turn on only one of the memory registers.

The data is then applied on the data lines and it is stored into the enabled register.

The length total number of locations is a function of the number of address lines. Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc. The chip will only work if an active signal is applied on that input. These address lines are decoded to generate the 2n necessary CS inputs for the memory chips to be used.

We will need to use 2 inputs and a decoder to identify which chip will be used at what time. The resulting design would now look like the one on the following slide. An example for the address range and its relationship to the memory chips would be the Post Office Boxes in the post office.

Boxes to are in group 0, boxes to are in group 1 and so on.

Intel 8085

We can look at the box number as if it is made up of two pieces: The upper digit of the box number identifies the group and the lower two digits identify the box within the group. So, it can address a total of 64K memory locations.

If we use memory chips with 1K locations each, then we will need 64 such chips. The 1K memory chip needs 10 address lines to uniquely identify the 1K locations.

Keep in mind that the 10 address lines on the chip gives a range of 00 to 11 or H to 3FFH for each of the chips. The memory chip in this example would require the following circuit on its chip select input: Changing the combination of the address bits connected to the chip select changes the address range for the memory chip.

Low-Order Address Lines The address lines from a microprocessor can be classified into two types: This classification is highly dependent on the memory system design. Lets look at memory width. We said that the width is the number of bits in each memory word. We have been assuming so far that our memory chips have the right width.

How would you design a byte wide memory system using these chips? One chip will supply 4 of the data bits per address and the other chip supply the other 4 data bits for the same address.

The interrupt process should be enabled using the EI instruction. The checks for an interrupt during the execution of every instruction. The Non-Vectored Interrupt Process 6. When the microprocessor executes the RST instruction received from the device, it saves the address of the next instruction on the stack and jumps to the appropriate entry in the IVT.

The IVT entry must redirect the microprocessor to the actual service routine. The service routine must include the instruction EI to re-enable the interrupt process. At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.

Therefore, the INTR must remain active for Otherwise, the microprocessor will be interrupted again. Therefore, the answer is: Interrupt Vector RST 5. Masking RST 5. Maskable Interrupts RST7.

If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop.

The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table. When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack.

The microprocessor jumps to the specific service routine. Set the interrupt masks so that RST5. Read Interrupt Mask — Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and mask. Set the mask to enable RST6. Accumulator M7. MSE M7. Interfacing the A to the Dev. After that, the following sequence occurs:

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